{"title":"Dawit Tekie Teclemariam","description":null,"products":[{"product_id":"long-dark-trail-book-dawit-tekie-teclemariam-9781528905343","title":"The Long Dark Trail","description":"\u003cp\u003eChapter 1. Introduction.\u003c\/p\u003e\u003cp\u003eChapter 2. Design using CMOS.\u003c\/p\u003e\u003cp\u003eChapter 3. ASIC design synthesis for combinational design (RTL using VHDL).\u003c\/p\u003e\u003cp\u003eChapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL).\u003c\/p\u003e\u003cp\u003eChapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL). \u003c\/p\u003e\u003cp\u003eChapter 6. ASIC design guidelines. \u003c\/p\u003e\u003cp\u003eChapter 7. ASIC RTL Verification. \u003c\/p\u003e\u003cp\u003eChapter 8. FSM using VHDL and synthesis. \u003c\/p\u003e\u003cp\u003eChapter 9. ASIC design improvement techniques.\u003c\/p\u003e\u003cp\u003eChapter 10. ASIC Synthesis using Synopsys DC.\u003c\/p\u003e\u003cp\u003eChapter 11. Design for Testability.\u003c\/p\u003e\u003cp\u003eChapter 12. Static timing analysis.\u003c\/p\u003e\u003cp\u003eChapter 13. Multiple Clock domain designs.\u003c\/p\u003e\u003cp\u003eChapter 14. Low power ASIC design.\u003c\/p\u003e\u003cp\u003eChapter 15. ASIC Physical design.\u003cbr\u003e\u003c\/p\u003e","brand":"WoB","offers":[{"title":"GB \/ NEW \/ GARDNERS","offer_id":49742309490961,"sku":"NGR9781528905343","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/1528905342.jpg?v=1751212708"}],"url":"https:\/\/www.worldofbooks.com\/collections\/author-books-by-dawit-tekie-teclemariam.oembed","provider":"World of Books ","version":"1.0","type":"link"}