SystemVerilog for Verification
SystemVerilog for Verification
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Zusammenfassung
It also reviews SystemVerilog 3.0 topics such as interfaces and data types.This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.
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SystemVerilog for Verification by Chris Spear
The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs.| SKU | Nicht verfügbar |
| ISBN 13 | 9781441945617 |
| ISBN 10 | 144194561X |
| Titel | SystemVerilog for Verification |
| Autor | Chris Spear |
| Buchzustand | Nicht verfügbar |
| Bindungsart | Paperback |
| Verlag | Springer-Verlag New York Inc. |
| Erscheinungsjahr | 2010-11-05 |
| Seitenanzahl | 429 |
| Hinweis auf dem Einband | Die Abbildung des Buches dient nur Illustrationszwecken, die tatsächliche Bindung, das Cover und die Auflage können sich davon unterscheiden. |
| Hinweis | Nicht verfügbar |