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Source-Synchronous Networks-On-Chip Ayan Mandal

Source-Synchronous Networks-On-Chip By Ayan Mandal

Source-Synchronous Networks-On-Chip by Ayan Mandal


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Summary

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Source-Synchronous Networks-On-Chip Summary

Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling by Ayan Mandal

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Table of Contents

Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.

Additional information

NLS9781493948178
9781493948178
1493948172
Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling by Ayan Mandal
New
Paperback
Springer-Verlag New York Inc.
2016-08-23
143
N/A
Book picture is for illustrative purposes only, actual binding, cover or edition may vary.
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