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Low-Power High-Level Synthesis for Nanoscale CMOS Circuits By Saraju P. Mohanty

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits by Saraju P. Mohanty

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Summary

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits Summary

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits by Saraju P. Mohanty

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Table of Contents

High-Level Synthesis Fundamentals.- Power Modeling and Estimation at Transistor and Logic Gate Levels.- Architectural Power Modeling and Estimation.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.- Conclusions and Future Direction.

Additional information

NLS9781441945549
9781441945549
1441945547
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits by Saraju P. Mohanty
New
Paperback
Springer-Verlag New York Inc.
2010-11-05
302
N/A
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