{"title":"J Bhasker","description":null,"products":[{"product_id":"a-verilog-hdl-primer-book-j-bhasker-9780965039178","title":"A Verilog HDL Primer","description":"The longstanding debate over the optimal duration of exclusive breastfeeding has centered on the so-called weanling's dilemma in developing countries: the choice between the known protective effect of exclusive breastfeeding against infectious morbidity and the (theoretical) insufficiency of breast milk alone to satisfy the infant's energy and micronutrient requirements beyond 4 months of age.\u003cbr\u003e\u003cbr\u003eThe primary objective of this review is to assess the effects on child health, growth, and development, and on maternal health, of exclusive breastfeeding for 6 months vs exclusive breastfeeding for 3-4 months with mixed breastfeeding (introduction of complementary liquid or solid foods with continued breastfeeding) thereafter through 6 months.","brand":"WoB","offers":[{"title":"GB \/ VERY_GOOD \/ INTERNAL","offer_id":49590198960401,"sku":"GOR013510285","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/096503917X.jpg?v=1750788502"},{"product_id":"verilog-hdl-synthesis-a-practical-primer-book-j-bhasker-9780965039154","title":"Verilog Hdl Synthesis: A Practical Primer","description":"Describes a step wise process of assessment, planning, and action that can be used to improve disability prevention and rehabilitation within the context of primary health care. Aware of the constraints often faced in district level services, the guide concentrates on measures that can be taken without the need for additional staff and without creating an excessive burden on time. Most activities described can be completed in the course of a one-day workshop. Throughout, numerous practical examples are used to illustrate how the process actually works in practice and the types of community problems it can address. \u003cbr\u003eThe guide, which is intended for district health and rehabilitation managers, has six chapters. The first explains how to use a one-day workshop to launch a district initiative for disability prevention and rehabilitation. Chapter two, on information gathering, explains pertinent sources of readily available information, and offers advice on how to use questionnaires and interviews to gather additional information. A time frame of six months is suggested for this research phase. Chapter three explains how to involve the community in the identification of problems and the planning of action. The remaining chapters cover assessment and planning at the district health level, monitoring and supervision of the current system for disability prevention and rehabilitation, and collaboration with other sectors, such as education, social services and labor, which can contribute to disability prevention and rehabilitation.","brand":"WoB","offers":[{"title":"US \/ VERY_GOOD \/ SBYB","offer_id":49798374981905,"sku":"CIN0965039153VG","price":0.0,"currency_code":"GBP","in_stock":false},{"title":"US \/ WELL_READ \/ SBYB","offer_id":50374164447505,"sku":"CIN0965039153A","price":0.0,"currency_code":"GBP","in_stock":false},{"title":"US \/ GOOD \/ SBYB","offer_id":50374166839569,"sku":"CIN0965039153G","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0965039153.jpg?v=1750819667"},{"product_id":"exchange-format-handbook-book-j-bhasker-9780965039130","title":"The Exchange Format Handbook","description":"Exchange formats demystified with clear and concise examples. Reading the book will give you the power to understand these formats faster. The book describes DEF, LEF, PDEF, SDF, SPEF and VCD. It describes what is in the standard, what its format looks like and clear explanations of its semantics.","brand":"WoB","offers":[{"title":"US \/ WELL_READ \/ SBYB","offer_id":50374160449809,"sku":"CIN0965039137A","price":0.0,"currency_code":"GBP","in_stock":false},{"title":"US \/ NEW \/ INGRAM","offer_id":51141458460945,"sku":"NIN9780965039130","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0965039137.jpg?v=1750948490"},{"product_id":"systemc-primer-second-edition-book-j-bhasker-9780984629206","title":"A SystemC Primer, Second Edition","description":"DESCRIPTION: (This softcover edition of the book has no accompanying CD). This is a beginner's book on SystemC targeted for both system designers as well as logic designers. Designers who already know VHDL or Verilog HDL will find the book very easy to read and learn about SystemC. Designers can in a very short time start writing SystemC models and simulating them with the information provided in the book. An excellent foreword has been provided by Stan Krolikoski, the Open SystemC Initiative Chairman --  ...a primer that gradually introduces the reader to the complexities of SystemC by reference to common digital design concepts ... REVIEW: Is easy to understand for anyone with digital logic design background . . . suitable as an introduction book to SystemC . . . Examples are very helpful - Xiaoyan Huang I enjoyed reading the SystemC Primer book. It was very easy to read and the examples were excellent. I feel like I have a good understanding of the language. I felt that the examples showed the positive attributes of the new language specifically the parameterization of models so they can be reusable. By using the examples the designer can focus more on the design itself and not the language - Jean Witinski This is a very useful book for those interested in SystemC for hardware design. It has many practical examples and gives pragmatic advice on what is possible with hardware synthesis - Grant Martin, Fellow, Cadence Labs This book provides an excellent introduction to SystemC. SystemC concepts are clearly explained and illustrated with practical examples. It is a must read for people interested in modeling hardware in SystemC - Abhijit Ghosh, Synopsys This is definitely a reference for designers who want to learn SystemC. Numerous examples guide the reader towards a sound understanding of the language. Higher level SystemC features are introduced and not kept aside. Bottom line, a very good book to SystemC . . .  - Yves Vanderperren, Alcatel Microelectronics Excellent introduction to SystemC constructs explained with detailed examples, complete with corresponding logic diagrams. A must for every SystemC designer's desk - Sanjiv Narayan I enjoyed reading it. Recommended to designers learning SystemC for modeling and synthesis . . . it will also be welcomed on both graduate and advanced undergraduate courses - David Long, Doulos Well suited as a text book for students and a great value for hardware designers that want to get started with SystemC - Bernhard Niemann, Fraunhofer Institute for Integrated Circuits","brand":"WoB","offers":[{"title":"GB \/ VERY_GOOD \/ INTERNAL","offer_id":50919860142353,"sku":"GOR014123370","price":0.0,"currency_code":"GBP","in_stock":false},{"title":"US \/ NEW \/ INGRAM","offer_id":52740773249297,"sku":"NIN9780984629206","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0984629203.jpg?v=1751267427"},{"product_id":"verilog-hdl-primer-third-edition-book-j-bhasker-9780984629244","title":"A Verilog HDL Primer, Third Edition","description":null,"brand":"WoB","offers":[{"title":"- \/ - \/ -","offer_id":51010420769041,"sku":"","price":0.0,"currency_code":"GBP","in_stock":true},{"title":"US \/ NEW \/ INGRAM","offer_id":51010424275217,"sku":"NIN9780984629244","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0984629246.jpg?v=1750851741"},{"product_id":"systemverilog-primer-book-j-bhasker-9780984629237","title":"A SystemVerilog Primer","description":null,"brand":"WoB","offers":[{"title":"US \/ NEW \/ INGRAM","offer_id":51010596929809,"sku":"NIN9780984629237","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0984629238.jpg?v=1751078054"},{"product_id":"static-timing-analysis-for-nanometer-designs-book-j-bhasker-9781441947154","title":"Static Timing Analysis for Nanometer Designs","description":"iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.","brand":"WoB","offers":[{"title":"- \/ - \/ -","offer_id":51026418893073,"sku":"","price":0.0,"currency_code":"GBP","in_stock":true},{"title":"US \/ NEW \/ INGRAM","offer_id":51026420924689,"sku":"NIN9781441947154","price":0.0,"currency_code":"GBP","in_stock":false},{"title":"GB \/ NEW \/ INGRAM","offer_id":52684772147473,"sku":"NLS9781441947154","price":0.0,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/1441947159.jpg?v=1751337708"},{"product_id":"static-timing-analysis-for-nanometer-designs-book-j-bhasker-9780387938196","title":"Static Timing Analysis for Nanometer Designs","description":"iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.","brand":"WoB","offers":[{"title":"- \/ - \/ -","offer_id":51141432181009,"sku":"","price":0.0,"currency_code":"GBP","in_stock":true},{"title":"US \/ NEW \/ INGRAM","offer_id":51141433458961,"sku":"NIN9780387938196","price":0.0,"currency_code":"GBP","in_stock":false},{"title":"GB \/ NEW \/ INGRAM","offer_id":52120885526801,"sku":"NLS9780387938196","price":0.0,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0387938192.jpg?v=1751292568"},{"product_id":"vhdl-synthesis-primer-book-j-bhasker-9780965039109","title":"A VHDL Synthesis Primer","description":null,"brand":"WoB","offers":[{"title":"- \/ - \/ -","offer_id":51697792581905,"sku":"","price":0.0,"currency_code":"GBP","in_stock":true},{"title":"US \/ GOOD \/ SBYB","offer_id":51697793106193,"sku":"CIN0965039102G","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/0965039102.jpg?v=1751364335"},{"product_id":"a-verilog-hdl-primer-book-bhasker-j-9780965039161","title":"A Verilog Hdl Primer","description":null,"brand":"WoB","offers":[{"title":"US \/ GOOD \/ SBYB","offer_id":52085295350033,"sku":"CIN0965039161G","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/9780965039161.jpg?v=1756816627"},{"product_id":"verilog-hdl-synthesis-a-practical-primer-book-j-bhasker-9780984629220","title":"Verilog HDL Synthesis, A Practical Primer","description":null,"brand":"WoB","offers":[{"title":"US \/ NEW \/ INGRAM","offer_id":52740912283921,"sku":"NIN9780984629220","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/9780984629220.jpg?v=1782826969"},{"product_id":"vhdl-synthesis-primer-second-edition-book-j-bhasker-9780984629213","title":"A VHDL Synthesis Primer, Second Edition","description":"Learn to model for synthesis using VHDL. See the details of how VHDL gets translated into logic gates in this book. Also, see how hardware elements are described in synthesizable VHDL. This book is a must primer for anyone who is beginning to learn synthesis using VHDL. A chapter on verification explains the many causes of simulation mismatches between pre and post synthesis models and how to avoid these. Modeling guidelines are also provided to help improve synthesis results.","brand":"WoB","offers":[{"title":"- \/ - \/ INTERNAL","offer_id":53251505783057,"sku":null,"price":0.0,"currency_code":"GBP","in_stock":true},{"title":"US \/ NEW \/ INGRAM","offer_id":53251506012433,"sku":"NIN9780984629213","price":0.0,"currency_code":"GBP","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0784\/4072\/6801\/files\/9780984629213.jpg?v=1773584829"}],"url":"https:\/\/www.worldofbooks.com\/en-au\/collections\/author-books-by-j-bhasker.oembed","provider":"World of Books ","version":"1.0","type":"link"}