On-Chip Networks by Natalie Enright Jerger
Provides a short synthesis of the critical concepts in on-chip network design. This volume is a resource for both understanding on-chip network basics and for providing an overview of state of the-art research in on-chip networks.
Jerger, Natalie Enright: - Natalie Enright Jerger is an Associate Professor and the Percy Edward Hart Professor of Electrical and Computer Engineering in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. She completed her Ph.D. at the University of Wisconsin-Madison in 2008. She received her Master of Science degree from the University of Wisconsin-Madison and Bachelor of Science in Computer Engineering from Purdue University in 2004 and 2002, respectively. Her research interests include multi- and many-core architectures, on-chip networks, cache coherence protocols, memory systems, and approximate computing. Her research is supported by NSERC, Intel, CFI, AMD, and Qualcomm. She was awarded an Alfred P. Sloan Research Fellowship in 2015, Borg Early Career Award in 2015, MICRO Hall of Fame in 2015, the Ontario Professional Engineers Young Engineer Medal in 2014, and the Ontario Ministry of Research and Innovation Early Researcher Award in 2012.
| SKU | Unavailable |
| ISBN 13 | 9781627059145 |
| ISBN 10 | 1627059148 |
| Title | On-Chip Networks |
| Author | Natalie Enright Jerger |
| Series | Synthesis Lectures On Computer Architecture |
| Condition | Unavailable |
| Binding Type | Paperback |
| Publisher | Morgan & Claypool Publishers |
| Year published | 2017-06-30 |
| Number of pages | 210 |
| Cover note | Book picture is for illustrative purposes only, actual binding, cover or edition may vary. |
| Note | Unavailable |