SystemVerilog for Verification
SystemVerilog for Verification
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Résumé
It also reviews SystemVerilog 3.0 topics such as interfaces and data types.This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.
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SystemVerilog for Verification by Chris Spear
The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs.| SKU | Non disponible |
| ISBN 13 | 9781441945617 |
| ISBN 10 | 144194561X |
| Titre | SystemVerilog for Verification |
| Auteur | Chris Spear |
| État | Non disponible |
| Type de reliure | Paperback |
| Éditeur | Springer-Verlag New York Inc. |
| Année de publication | 2010-11-05 |
| Nombre de pages | 429 |
| Note de couverture | La photo du livre est présentée à titre d'illustration uniquement. La reliure, la couverture ou l'édition réelle peuvent varier. |
| Note | Non disponible |