Design Through Verilog HDL by T R Padmanabhan
Verilog provides platforms for designs to be described at different layers of complexity, combine them in a seamless manner, test them at every stage and build up a bug-free design. This book intends to guide readers to master Verilog as an HDL and use it for design.
"…this book is surely welcome…due to its simple but efficient structure, the book can be used both in academia and in industry" (IEEE Circuits & Devices, July/August 2006)
“...ideally suited for teaching digital hardware design techniques using a low-level programming language...highly recommended...” (Choice, Vol. 41, No. 8, April 2004)
"…enables readers to master Verilog as an HDL for design...engages the readers at every stage through the variety and number of examples." (IEEE Solid-State Circuits Society Newsletter, January 2004)
T. R. PADMANABHAN, PhD, is Dean-Engineering, Amrita Institute of Technology, Amrita Vishwa Vidyapeetham, (Amrita University), Ettimadai (PO), Coimbatore, India. He is a Senior Member of IEEE as well as a Fellow of both India’s IE and IETE.
B. BALA TRIPURA SUNDARI is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology. She is a senior faculty member in the microelectronics center at the institute. She is a member of India’s IETE and ISTE.
| SKU | Unavailable |
| ISBN 13 | 9780471441489 |
| ISBN 10 | 0471441481 |
| Title | Design Through Verilog HDL |
| Author | T R Padmanabhan |
| Condition | Unavailable |
| Binding Type | Hardback |
| Publisher | Wiley-IEEE Press |
| Year published | 2003-11-25 |
| Number of pages | 472 |
| Cover note | Book picture is for illustrative purposes only, actual binding, cover or edition may vary. |
| Note | Unavailable |