Formal Verification
Formal Verification
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Formal Verification by Erik Seligman
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
| SKU | Unavailable |
| ISBN 13 | 9780323956123 |
| ISBN 10 | 0323956122 |
| Title | Formal Verification |
| Author | Erik Seligman |
| Condition | Unavailable |
| Binding Type | Paperback |
| Publisher | Elsevier Science & Technology |
| Year published | 2023-05-26 |
| Number of pages | 424 |
| Cover note | Book picture is for illustrative purposes only, actual binding, cover or edition may vary. |
| Note | Unavailable |